gcc make: *** Error 1 error

An alternative is installing make via Chocolatey (as pointed out by Vasantha Ganesh K). However, number of cores+a few is typically a good approximation. The only way to know for sure is experimentation. It may behoove you to read some of the comments before taking action. The usual “opposite” of gmake is BSD make, which will tend to be make on BSD systems, unsurprisingly. If you want to see what BSD make is like, on Debian derivatives it’s available as apt-get install pmake.

How can I pass a macro definition from “make” command line arguments (-D) to C source code?

With that flag you can execute a makefile with a name other than makefile. Because you do want to override your Makefile’s CFLAGS, and not just the environment (which has a lower priority with regard to Makefile variables). You can also create a symbolic link from “make” to “mingw32-make”, or copying and changing the name of the file. I would not recommend the options before; they will work until you do changes on the MinGW installation. Note that you might not be able to select your environment.

make: *** Error 1 error duplicate

The idea behind this is that all cores have their own thread and there is one additional managing thread that handles the targets and which is next to be plinko casino game built. If you set the allowed number of threads too high, it is not possible to schedule each thread on its own core. Additional scheduling (context) switches are required to let all threads execute. This additional resource usage obviously result in lower performance.

Answers 4

Variables in make can come from the environment in which make is run. Every environment variable that make sees when it starts up is transformed into a make variable with the same name and value. However, an explicit assignment in the makefile, or with a command argument, overrides the environment. Now I need to allow the user of my makefile to be able to pass arbitrary macro definitions from the “make.exe commandline” to “source code” right away, without having to change anything in the makefile. And be sure to use $(CFLAGS) in your compile command in the Makefile. As @jørgensen mentioned, putting the variable assignment after the make command will override the CFLAGS value already defined in the Makefile.

Passing additional variables from command line to make

You can either set -j or even higher -j so that compilation can happen in parallel. All relative paths in the makefile will be relative to your current directory and not the directory of the makefile. I’m following the instructions of someone whose repository I cloned to my machine. I want to use the make command as part of setting up the code environment, but I’m using Windows. Connect and share knowledge within a single location that is structured and easy to search.

If it’s from Linux, you might need to use a real Linux or WSL. If make can run parallel builds, it will launch up to 6 simultaneous compilation process (e.g. 6 calls to gcc). The -j option is only use to speed up application build, it determines how many jobs make can spawn for the build.